1. Field of the Invention
The present invention relates to a driving apparatus for an AC drive type plasma display panel (hereinafter called xe2x80x9cPDPxe2x80x9d) or a display panel having capacitive loads such as electroluminescence (hereinafter called xe2x80x9cELxe2x80x9d) elements.
2. Description of the Related Background Art
Display apparatuses which use flat panels display devices of a self-emitting type such as a PDP or EL panel, are manufactured as on-wall TV""s.
FIG. 1 is a diagram showing a schematic structure of the display apparatus.
In FIG. 1, a PDP 10 has row electrodes Y1 to Yn and row electrodes X1 to Xn, each pair of which corresponds to a single one of rows of one screen (the first row to the n-th row). Further formed on the PDP 10 are column electrodes Z1 to Zm which correspond to the respective columns of one screen (the first column to the m-th column) with an unillustrated dielectric layer and discharge space provided in between and which run perpendicular to those row electrode pairs. A single discharge cell C(i,j) is formed at each intersection of one pair of row electrodes (X, Y) and a single column electrode Z.
A row electrode driver 30 first generates reset pulses RPY of a positive voltage as shown in FIG. 2 and simultaneously applies those pulses to the row electrodes Y1-Yn. At the same time, a row electrode driver 40 generates reset pulses RPx of a negative voltage and simultaneously applies those pulses to the row electrodes X1-Xn.
The simultaneous application of those reset pulses RPx and RPy causes all the discharge cells of the PDP 10 to be excited and discharged, generating charge particles, and a predetermined amount of wall charges are evenly formed in the dielectric layers of the entire discharge cells after the discharging is finished (reset cycle).
After the reset cycle, a column electrode driver 20 generates pixel data pulses DP1 to DPn respectively corresponding to the first row to the n-th row of the screen and sequentially applies the pixel data pulses to the column electrodes Z1-Zm as shown in FIG. 2. In accordance with the application timing of the pixel data pulses DP1-DPn, the row electrode driver 30 generates a scan pulse SP of a negative voltage and sequentially applies the scan pulse SP to the row electrodes Y1-Yn, as shown in FIG. 2.
In any discharge cells in the row electrode to which the scan pulse SP has been applied, discharging occurs and most of the wall charges are lost. Those discharge cells are cells to which the pixel data pulses of a positive voltage have also been applied at the same time. Since no discharging occurs in those discharge cells which have been applied with the scan pulse SP but not the pixel data pulses of a positive voltage, the wall charges remain. The discharge cells in which the wall charges have stayed become light-emitting discharge cells while those from which the wall charges have been lost become non-emitting discharge cells (address cycle).
When the address cycle ends, the row electrode drivers 30 and 40 continuously apply sustain pulses IPy of a positive voltage to the row electrodes Y1-Yn and continuously apply sustain pulses IPx of a positive voltage to the row electrodes X1-Xn at timings different from the application timings of the sustain pulses IPy.
The light-emitting discharge cells where the wall charges have remained repeat discharge emission and maintain the light emission over a period in which the sustain pulses IPx and IPy are alternately applied (sustain discharge cycle).
A drive control circuit 50 shown in FIG. 1 generates various switching signals for generating various drive pulses as shown in FIG. 2 based on the timing of supplied video signals and supplies the switching signals to the column electrode driver 20 and the row electrode drivers 30 and 40.
The column electrode driver 20 and the row electrode drivers 30 and 40 generate the various drive pulses shown in FIG. 2 according to the switching signals supplied from the drive control circuit 50.
FIG. 3 is a diagram illustrating a drive pulse generator which is provided in the row electrode driver 30 and generates the reset pulse RPy and the sustain pulse IPy.
In FIG. 3, the drive pulse generator is provided with a capacitor C1 having one end grounded to a PDP ground potential Vs as the ground potential of the PDP 10.
A switching element S1 is open when a switching signal SW1 having a logic level xe2x80x9c0xe2x80x9d is being supplied from the drive control circuit 50. When the logic level of the switching signal SW1 is xe2x80x9c1xe2x80x9d, however, the switching element S1 is closed, thereby applying the potential produced on the other end of the capacitor C1 to a line 2 via a coil L1 and a diode D1. As a result, the capacitor C1 starts discharging and the potential generated by the discharge is applied to the line 2.
A switching element S2 is open when a switching signal SW2 having a logic level xe2x80x9c0xe2x80x9d is being supplied from the drive control circuit 50. When the logic level of the switching signal SW2 is xe2x80x9c1xe2x80x9d, on the other hand, the switching element S2 is closed, thereby applying the potential on the line 2 to the other end of the capacitor C1 via a coil L2 and a diode D2. That is, the capacitor C1 is charged with the potential on the line 2.
A switching element S3 is open when a switching signal SW3 of a logic level xe2x80x9c0xe2x80x9d is being supplied from the drive control circuit 50. When the logic level of the switching signal SW3 is xe2x80x9c1xe2x80x9d, however, the switching element S3 is closed, thereby applying a positive terminal potential Vc of a DC power supply B1 to the line 2. The negative terminal of the DC power supply B1 is applied with the PDP ground potential Vs.
A switching element S4 is open when a switching signal SW4 of a logic level xe2x80x9c0xe2x80x9d is being supplied from the drive control circuit 50. When the logic level of the switching signal SW4 is xe2x80x9c1xe2x80x9d, the switching element S4 is closed, thereby applying the PDP ground potential Vs to the line 2.
The line 2 is connected to the row electrodes Y of the PDP 10 which has a capacitive element CO. That is, n circuits each as shown in FIG. 3 corresponding to the row electrodes Y1-Yn are provided in the row electrode driver 30.
FIG. 4 is a diagram showing timing of the switching signals SW1-SW4 which the drive control circuit 50 supplies to the row electrode driver 30 shown in FIG. 3 in order to produce the sustain pulse IPy shown in FIG. 2 on the line 2.
As shown in FIG. 4, since only the switching signal SW4 of the switching signals SW1-SW4 has a logic level xe2x80x9c1xe2x80x9d first, the switching element S4 is closed to apply the PDP ground potential Vs to the line 2. During the period, the potential on the line 2 is the PDP ground potential Vs, i.e., 0 V.
When the logic levels of the switching signals SW4 and SW1 are respectively switched to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, only the switching element S1 is closed, causing the charges stored in the capacitor C1 to be discharged. Consequently, the current transiently flows across the coil L1 with a waveform as illustrated in FIG. 4. The current flows into the PDP 10 through the diode D1, the switching element S1 and the line 2, so that the capacitive element C0 is charged. The potential on the line 2 gradually increases as shown in FIG. 4.
When the logic levels of the switching signals SW1 and SW3 are respectively switched to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, only the switching element S3 is closed, so that the positive terminal potential Vc of a DC power supply B1 is applied to the line 2. Consequently, the potential on the line 2 is fixed to Vc as shown in FIG. 4.
When the logic levels of the switching signals SW2 and SW3 are respectively switched to xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, only the switching element S2 is closed, so that a negative current transiently flows across the coil L2 with a waveform as illustrated in FIG. 4. That is, the capacitive element C0 of the PDP 10 that has been charged in the above-described manner discharges and its current flows into the capacitor C1 through the line 2, the coil L2, the diode D2 and the switching element S2 and is stored there. As a result, the potential on the line 2 gradually decreases as shown in FIG. 4.
Through the above operation, the sustain pulse IPy of a positive voltage as shown in FIG. 4 is applied to the line 2.
As the structure illustrated in FIG. 3 needs four switching elements S1-S4, however, the circuit scale becomes disadvantageously large.
Further, the circuit cannot be used in generating the pixel data pulses to the column electrodes that demand a fast operation.
Accordingly, it is an object of the present invention to provide a driving apparatus for a display panel, which can operate fast with lower power consumption and with a simple structure.
According to the present invention, there is provided a driving apparatus for a display panel having a plurality of row electrodes and a plurality of column electrodes intersecting the row electrodes, for generating a drive pulse to be applied to each of the electrodes. The driving apparatus comprises a DC power supply for generating a DC voltage and having a positive terminal and a negative terminal one of which is applied with a reference potential; a coil having a first end connected to the other terminal of the DC power supply; and switching means for alternately making a connection and disconnection between the first end of the coil and the other terminal of the DC power supply, whereby a potential change appearing on a second end of the coil is used as the drive pulse.